This invention relates to nonvolatile semiconductor memory devices, more particularly, to an electrically-erasable, electrically-programmable ROM (read-only-memory) of the floating-gate type and to a method for making such a device.
EPROMs, or electrically-programmable ROMs, are nonvolatile memory field-effect devices with floating-gate structures. In general, an EPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing high current through the source-drain path and charging of the floating gate by hot electrons. The EPROM type of device is usually erased by ultraviolet light, which requires a device package having a quartz window above the semiconductor chip. Packages of this type are expensive in comparison with the plastic packages ordinarily used for other memory devices such as DRAMs (dynamic-random-access-memories). For this reason, EPROMs are generally more expensive than plastic-packaged devices. EPROM devices of this type, and methods of manufacture, are disclosed in U.S. Pat. Nos. 3,984,822; 4,142,926; 4,258,466; 4,376,947; 4,326,331; 4,313,362; 4,373,248; or 4,750,024; for example.
EEPROMs, or electrically-erasable, electrically-programmable ROMs, have been manufactured by various processes, and usually require much larger cell sizes than standard EPROMs. The structures and the manufacturing processes are usually more complex. EEPROM arrays can be mounted in opaque plastic packages that reduce the packaging cost. Nevertheless, EEPROM arrays have been more expensive on a per-bit basis, in comparison with EPROM arrays, due to larger cell size and to more complex manufacturing processes.
As compared to EPROM arrays, EEPROM arrays require a wider range of voltage sources for the purposes of programming, reading and erasing. Because the bitlines are connected to many cells in the array other than the cell being programmed, read, or erased, the wider range of voltages increases the possibility that one or more of the other cells will be inadvertently programmed or erased. The problem is particularly present in so-called "virtual-ground" arrays such as that disclosed in U.S. Pat. No. 4,281,397.
Flash EEPROMs have the advantage of smaller cell size in comparison with standard EEPROMs because the cells are not erased individually. Instead, the array of cells is erased in bulk.
Currently available flash EEPROMs require at least two external power supplies, one for programming and erasing and another for reading. Typically, a 12-volt power supply is used for programming and erasing and a 5-volt power supply is used during read operations. It is desirable, however, to employ a single relatively low-voltage supply for all of the programming, erasing and reading operations. For example, on-chip charge-pump techniques may be used to generate higher voltages from the 5-volt supply if the memory cells of the array are designed to be programmed and erased while drawing a relatively small current. In general, cells designed to use Fowler-Nordheim tunnelling for programming and erasing require relatively small current in comparison to the current required when using hot-electron programming.
The EEPROMs disclosed in co-pending U.S. patent applications Ser. No. 07/219,528; No. 07/219,529 and No. 07/219,530 provide greatly improved structures and methods for making cells having reduced size and ease of manufacture, resulting in a device requiring one relatively low-voltage (perhaps +5 v) external power supply for the chip. The devices of those inventions use Fowler-Nordheim tunnelling for erasure and for programming. The EEPROM disclosed in U.S. patent application Ser. No. 07/360,558 discloses a structure that does not include a split control gate, thereby decreasing the space required on an integrated circuit substrate as compared to a structure with a split gate, yet can be down-scaled in size and can be packaged in a less expensive opaque plastic package. However, removal of the split gate results in reading errors if some of the memory cells are over-erased.
The size of a memory cell structure may be decreased from that of the structure disclosed in U.S. patent application Ser. No. 07/360,558, for example, by forming cells such that pairs of cells share the same drain structure, as in U.S. patent application Ser. No. 07/374,381, also assigned to Texas Instruments Incorporated. The structure disclosed in that application uses a field-plate electrode to provide isolation between cells in a pair during programming, reducing the number of bitlines required per column of cells from two to only one and one-half. The channels of the cell structures described in the latter Application are divided into three sub-channel regions. The conductivities of the three series-connected regions are individually controlled by the field-plate electrode, the control gate, and the floating gate. However, the size of the memory cell may be further decreased, and the on-state conductivity of the memory cell may be improved, by eliminating the channel subregion controlled by the control gate.